Flash technology

The flash technology is evolving rapidly and new methods of improving its storage efficiency are appearing every 12 months in average. Let's examine the standard technology first and then examine some of the recent improvements appearing in the market.

Standard Flash Technology

Typical flash memory uses a single bit-per-cell. Each cell is characterized by a specific threshold voltage, or VT level. An electrical charge is stored on a floating gate of each cell. Within each cell, or transistor, two possible voltage levels exist determined by the amount of charge that is programmed or stored on the floating gate; if the amount of charge on the floating gate is above VT the cell is considered to have stored a "one" otherwise it has stored a "zero". These charges are trapped and do not leak out even when power is removed.

-Write Operation

Programming takes place in two phases. First the device is "erased " (all electrons on the floating gate are removed) then a precise charge is placed onto the floating gate of a given transistor. The analog voltage that exists across each flash cell is controlled by the amount of electrons injected in the floating gate. The transistors are placed in a matrix configuration that allows charge placement through the selection of a given column and row.

-Read Operation

During data read, the voltage level at the gate of each transistor is detected . A matrix organization of all transistors allows direct connections of each memory cell to a sense amplifier. The sense amplifier determines the voltage level of each memory cell and defines it as a one or a zero depending on whether it is above or below a threshold voltage.

The read operation does not stress the device and can be performed indefinitely whereas the write operation introduces some "wearing" of the device.

Multi-Level Cell Flash Technology

Multi-Level Cell (MLC) technology recently introduced by "Intel" enables storage of multiple bits per memory cell by charging the floating gate of a given transistor to different, but precisely controlled, levels. This technology takes advantage of the analog nature of a traditional flash cell by assigning a bit pattern to a specific voltage range. If for example, in the traditional flash memory, we sense the gate voltage and compare it to a threshold we can assign the binary value of 1 or zero depending we are above or below it:

Voltage Interpretation

Above
threshold 1
Below
threshold 0

In the MLC technology we can compare the gate voltage to a number of levels and assign for each case a binary pattern. In the case of 4 levels :

Voltage Binary Interpretation

level3 0,0
level 2 0,1
level 1 1,0
level 0 1,1

Thus a doubling of the cell memorizing ability has been achieved.

This method can be extrapolated to "n" levels. The number of levels that can be used is limited only by the accuracy of the voltage detection and comparison to a threshold. In addition, these levels must be compatible with the precision of charge placement onto the floating gate. It can be expected that the technology will evolve rapidly in creating more and more levels.

MLC effectively reduces cell area as well as the die size for a given density. This ultimately leads to a significantly reduced unit cost-per-megabyte. Today's MLC memory products are capable of storing two bits per memory cell.

Advantages and Disadvantages of Flash

As a device, Flash memory is considered equivalent to Dynamic Random Access memories or DRAM. Like a DRAM it allows random access to data and in-system reprogrammability. However contrary to DRAMs, Flash memory is non-volatile and can retain information without the help of external power (battery). This last point is of considerable importance and makes FLASH a "solid state" contender to the hard disk drive which is considered "electromechanical" and therefore sensitive to shocks vibrations and environmental conditions.

Flash can be compared to EEPROMS for speed but with the advantage of requiring lower power and lower voltage to operate (down to 2.2 volts) for read and write operation. Flash can even simultaneously be reading one sector while programming or erasing another which EEPROM cannot.

Flash cannot be rewritten on a byte basis , it must be erased first. Erasure is performed on a block by block basis. However it is important to note that contrary to other memory devices a "wearing" process occurs each time an erase cycle has been performed. A typical flash is specified for 100.000 cycles operation. This specification is important in determining its suitability to a given application and the method best appropriate for efficient usage of the device.

Flash memories are difficult to fabricate when compared to DRAMs. In addition the recent dramatic cost drop of DRAMS due to a market oversupply makes this device a very attractive choice when compared to Flash.

MLC Technology Advantages

Not only is MLC memory valuable as a digital media, but advantages such as direct access to each cell, permit reliable charge placement, sensing, and storage. There is also a great advantage in cost. It is well known that cost relates directly to die size. The smaller the die size, the lower the cost. Dramatic cost breaks are associated with the MLC technology approach because, at two bits-per-cell, the density of the device is doubled without increasing the die size. This becomes even more apparent at three bits-per-cell, where the density of bits-per-cell will triple without significantly increasing die size.

Flash is offered today at a 0.5 um geometry. In 1998, 0.35 and even 0.25 um geometry will be available with a subsequent increase in chip capacity. In addition the "MultiLevel Cell Technology" will further increase the chip capacity. The current 8 Mbyte device will be replaced by 16, 32 or even 64 Mbyte devices in 2 to 3 years.

Product Samples

Producers reporting the largest shipments include Intel, SanDisk, Toshiba and AMD

By: Farid Neema and Gaston Palombo

This Paper was produced by:
PERIPHERAL CONCEPTS, INC.
351 Hitchcock Way, Suite #B-200
Santa Barbara, California, 93105
Tel: (805) 563-9491
fneema@periconcepts.com